Michael Roberge

According to our database, Michael Roberge authored at least 5 papers between 2007 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory.

Eric Hunt-Schroeder, Darren Anand, Edward Hwang, Aaron Cummings, Matthew Deming, Michael Roberge, Michael Ziegerhofer

Proceedings of the 28th IEEE North Atlantic Test Workshop, 2019

2018

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.

Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2010

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.

Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007

Advancements in at-speed array BIST: multiple improvements.

Kevin W. Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin

Proceedings of the 2007 IEEE International Test Conference, 2007

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007