Darren Anand

According to our database, Darren Anand authored at least 13 papers between 2001 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory.

Eric Hunt-Schroeder, Darren Anand, Edward Hwang, Aaron Cummings, Matthew Deming, Michael Roberge, Michael Ziegerhofer

Proceedings of the 28th IEEE North Atlantic Test Workshop, 2019

2018

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.

Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2011

Embedded DRAM in 45-nm Technology and Beyond.

Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli

IEEE Des. Test Comput., 2011

2010

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.

Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Low Cost Test of High Bandwidth Embedded Memories.

Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.

John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva

IEEE J. Solid State Circuits, 2005

2004

Generating At-Speed Array Fail Maps with Low-Speed ATE.

Michael R. Nelms, Kevin W. Gorman, Darren Anand

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface.

Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier

IEEE J. Solid State Circuits, 2003

An On-Chip Self-Repair Calculation and Fusing Methodology.

Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater

IEEE Des. Test Comput., 2003

2002

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering.

John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek

IBM J. Res. Dev., 2002

2001

Embedded DRAM built in self test and methodology for test insertion.

Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Shared fuse macro for multiple embedded memory devices with redundancy.

Michael R. Ouellette, Darren Anand, Peter Jakobsen

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001