Paul M. Chau

Affiliations:
  • University of California, San Diego, USA


According to our database1, Paul M. Chau authored at least 43 papers between 1984 and 2014.

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Bibliography

2014
Constrained Sensor System Resolves Closely Spaced Obscured Low-SNR Sources Using Virtual Beamforming.
IEEE Trans. Instrum. Meas., 2014

2012
Low-Level Sinusoidal Signal Detection From a High-Resolution Virtual Spectral Image Using Autoregressive Vector Extrapolation.
IEEE Trans. Instrum. Meas., 2012

2006
Power aware attitude computation during rapid rotational motion.
IEEE Trans. Instrum. Meas., 2006

Objective Human Visual System Based Video Quality Assessment Metric for Low Bit-Rate Video Communication Systems.
Proceedings of the IEEE 8th Workshop on Multimedia Signal Processing, 2006

2002
Microarchitectural synthesis of performance-constrained, low-power VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2002

Reduce complexity hardware implementation of discrete wavelet transform for JPEG 2000 standard.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

2000
Robust image transmission over CDMA channels.
IEEE Trans. Consumer Electron., 2000

Image encryption for secure Internet multimedia applications.
IEEE Trans. Consumer Electron., 2000

Hardware/software implementation 3-way algorithm for image encryption.
Proceedings of the Security and Watermarking of Multimedia Contents II, 2000

Image encryption for multimedia applications.
Proceedings of the ISCA 15th International Conference Computers and Their Applications, 2000

1999
Conditional probability density function estimation with sigmoidal neural networks.
IEEE Trans. Neural Networks, 1999

A 1.2 GHz CMOS quadrature self-oscillating mixer.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

FPGA architecture for noise filters on a reconfigurable processor.
Proceedings of the Computers and Their Applications (CATA-99), 1999

Reconfigurable Hardware for Encryption.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding.
IEEE J. Solid State Circuits, 1998

A Feature Extraction Application on a Reconfigurable Image Processor.
Proceedings of the Image and Vision Computing New Zealand, International Conference, 1998

Blind signal separation with a projection pursuit index.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Reconfigurable Processing for Robust Navigation and Control (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Evolvable Hardware Control for Dynamic Reconfigurable and Adaptive Computing.
Proceedings of the Evolutionary Programming VII, 7th International Conference, 1998

1996
An extension to the SCI flow control protocol for increased network efficiency.
IEEE/ACM Trans. Netw., 1996

A wire length estimation technique utilizing neighborhood density equations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Casasent network density estimation.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems.
J. VLSI Signal Process., 1995

Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems.
IEEE Trans. Signal Process., 1995

A supervised learning neural network coprocessor for soft-decision maximum-likelihood decoding.
IEEE Trans. Neural Networks, 1995

Execution of a remote sensing application on a custom neurocomputer.
IEEE Trans. Neural Networks, 1995

1994
Rapid Prototyping of ASIC Based Systems.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network.
J. VLSI Signal Process., 1993

Parallel implementations of direction finding algorithms on networks of general purpose DSP processors.
Integr., 1993

A Hybrid Radial Basis Function Neurocomputer and Its Applications.
Proceedings of the Advances in Neural Information Processing Systems 6, 1993

Enhancing SCI's fairness protocol for increased throughput.
Proceedings of the 1993 International Conference on Network Protocols, 1993

Recursive least squares problem implementation on a generalized interconnection of DSP processors.
Proceedings of the IEEE International Conference on Acoustics, 1993

<i>Prime</i>: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Power dissipation of VLSI array processing systems.
J. VLSI Signal Process., 1992

Sigma-delta encoding for efficient equalization of prefilter based FIR filters.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Macropipelining based heterogeneous multiprocessor scheduling.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1991
A technique for realizing linear phase IIR filters.
IEEE Trans. Signal Process., 1991

Hierarchical Modeling of the VLSI Design Process.
IEEE Expert, 1991

1990
A neural network architecture for the decoding of long constraint length convolutional codes.
Proceedings of the IJCNN 1990, 1990

KINFIDA: an object-oriented model-based digital filter design assistant.
Proceedings of the 1990 International Conference on Acoustics, 1990

1989
VLSI for a Physical Model of Musical Instruments Oscillations.
Proceedings of the 1989 International Computer Music Conference, 1989

1987
A bit-serial floating-point complex multiplier-accumulator for fault-tolerant digital signal processing arrays.
Proceedings of the IEEE International Conference on Acoustics, 1987

1984
Digital signal processing capabilities of CUSP, a high performance bit-serial VLSI processor.
Proceedings of the IEEE International Conference on Acoustics, 1984


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