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Peifang Wu

Orcid: 0009-0003-5985-2398

According to our database1, Peifang Wu authored at least 3 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving -269.9-dB FoM<sub>Jitter-N-Area</sub>.
[BibTeX]
[DOI]
Haoyuan Gao
,
Yan Liu
,
Peifang Wu
,
Jiao Liu
,
Yiyun Mao
,
Xinyi Lin
,
Rui Yin
,
Ping Lu
,
Long Kong
,
Na Yan
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

2025
An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.
[BibTeX]
[DOI]
Yiyun Mao
,
Haoyuan Gao
,
Jin Shao
,
Xinyi Lin
,
Peifang Wu
,
Ping Lu
,
Hao Xu
,
Na Yan
IEEE Trans. Circuits Syst. II Express Briefs, April, 2025

2023
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.
[BibTeX]
[DOI]
Peifang Wu
,
Yan Liu
,
Xi Feng
,
Hao Xu
,
Na Yan
Proceedings of the 15th IEEE International Conference on ASIC, 2023


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