Yiyun Mao

According to our database, Yiyun Mao authored at least 4 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving -269.9-dB FoM_{Jitter-N-Area}.

Haoyuan Gao, Yan Liu, Peifang Wu, Jiao Liu, Yiyun Mao, Xinyi Lin, Rui Yin, Ping Lu, Long Kong, Na Yan

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

2025

An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.

Yiyun Mao, Haoyuan Gao, Jin Shao, Xinyi Lin, Peifang Wu, Ping Lu, Hao Xu, Na Yan

IEEE Trans. Circuits Syst. II Express Briefs, April, 2025

2023

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.

Yizhuo Wang, Jiahe Shi, Hao Xu, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao, Hao Min, Na Yan

IEEE J. Solid State Circuits, 2023

An ADPLL Design Model Based on LoRa IoT Application.

Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu, Na Yan

Proceedings of the 15th IEEE International Conference on ASIC, 2023