Yan Liu

According to our database, Yan Liu authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 6.8-GHz Fractional-N Pulse-Shaper-Based PLL Achieving -269.9-dB FoM_{Jitter-N-Area}.

Haoyuan Gao, Yan Liu, Peifang Wu, Jiao Liu, Yiyun Mao, Xinyi Lin, Rui Yin, Ping Lu, Long Kong, Na Yan

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

2024

A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.

Yan Liu, Haoyuan Gao, Hao Xu, Ping Lu, Na Yan

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.

Yizhuo Wang, Hao Xu, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications.

Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS.

Peifang Wu, Yan Liu, Xi Feng, Hao Xu, Na Yan

Proceedings of the 15th IEEE International Conference on ASIC, 2023