Peter Malík

According to our database, Peter Malík authored at least 23 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

From Anomaly Detection to Defect Classification.

Jaromír Klarák, Robert Andok, Peter Malík, Ivan Kuric, Mário Ritomský, Ivana Klacková, Hung-Yin Tsai

Sensors, January, 2024

2023

Crop Mapping without Labels: Investigating Temporal and Spatial Transferability of Crop Classification Models Using a 5-Year Sentinel-2 Series and Machine Learning.

Tomas Rusnak, Tomás Kasanický, Peter Malík, Ján Mojzis, Ján Zelenka, Michal Svicek, Dominik Abrahám, Andrej Halabuk

Remote. Sens., July, 2023

2021

StarCraft strategy classification of a large human versus human game replay dataset.

Stefan Kristofík, Matús Kasás, Peter Malík

Proceedings of the 16th Conference on Computer Science and Intelligence Systems, 2021

2020

Instance Segmentation Model Created from Three Semantic Segmentations of Mask, Boundary and Centroid Pixels Verified on GlaS Dataset.

Peter Malík, Kristína Knapová, Stefan Kristofík

Proceedings of the 2020 Federated Conference on Computer Science and Information Systems, 2020

StarCraft agent strategic training on a large human versus human game replay dataset.

Stefan Kristofík, Matús Kasás, Stefan Neupauer, Peter Malík

Proceedings of the 2020 Federated Conference on Computer Science and Information Systems, 2020

AI Architectures for Very Smart Sensors.

Peter Malík, Stefan Kristofík

Proceedings of the Convergence of Artificial Intelligence and the Internet of Things, 2020

2019

Universal framework for remote firmware updates of low-power devices.

Ondrej Kachman, Marcel Baláz, Peter Malík

Comput. Commun., 2019

Machine Learning and Deep Learning frameworks and libraries for large-scale data mining: a survey.

Giang Nguyen, Stefan Dlugolinsky, Martin Bobák, Viet D. Tran, Álvaro López García, Ignacio Heredia, Peter Malík, Ladislav Hluchý

Artif. Intell. Rev., 2019

2018

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement.

Stefan Kristofík, Marcel Baláz, Peter Malík

Microelectron. Reliab., 2018

Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults.

Stefan Kristofík, Peter Malík

Integr., 2018

2016

Dedicated Hardware for Complex Mathematical Operations.

Peter Malík

Comput. Informatics, 2016

Natural logarithm and division floating-point high throughput co-processor implemented in FPGA.

Peter Malík

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015

High Throughput Floating Point Exponential Function Implemented in FPGA.

Peter Malík

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

High Throughput Floating-Point Dividers Implemented in FPGA.

Peter Malík

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Dedicated hardware architecture for object tracking preprocessing implemented in FPGA.

Peter Malík

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2011

Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC.

Peter Malík

IET Circuits Devices Syst., 2011

2009

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.

Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Various MDCT implementations in 0.35µm CMOS.

Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

A Generic IP Core of the Identical Forward and Inverse 12/36-Point MDCT Architecture and an Architectural Model Simulation Toolbox.

Peter Malík

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Clockless Implementation of LEON2 for Low-Power Applications.

Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

An Improved MDCT IP Core Generator with Architectural Model Simulation.

Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

MDCT IP Core Generator with Architectural Model Simulation.

Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík

Proceedings of the IFIP VLSI-SoC 2006, 2006

FPGA Implementation of a Fast MDCT Algorithm.

Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006