Peter Petrov
According to our database1,
Peter Petrov
authored at least 59 papers
between 1991 and 2022.
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Bibliography
2022
Remote. Sens., 2022
2019
Forward Simulation of Multi-Frequency Microwave Brightness Temperature over Desert Soils in Kuwait and Comparison with Satellite Observations.
Remote. Sens., 2019
2017
Proceedings of the Foundations of Intelligent Systems - 23rd International Symposium, 2017
2015
Preliminary field results of soil moisture from Kuwait desert as a core validation site of SMAP satellite.
Proceedings of the 2015 IEEE International Geoscience and Remote Sensing Symposium, 2015
2013
J. Integr. Bioinform., 2013
2011
Dynamically Adaptive I-Cache Partitioning for Energy-Efficient Embedded Multitasking.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table.
IET Comput. Digit. Tech., 2011
2010
Low-Cost and Energy-Efficient Distributed Synchronization for Embedded Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Energy- and Performance-Efficient Communication Framework for Embedded MPSoCs through Application-Driven Release Consistency.
ACM Trans. Design Autom. Electr. Syst., 2010
ACM Trans. Embed. Comput. Syst., 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
I-cache configurability for temperature reduction through replicated cache partitioning.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Neural regulator design for parabolic distributed parameter systems with constraints in control.
Proceedings of the 5th IEEE International Conference on Intelligent Systems, 2010
Context-aware TLB preloading for interference reduction in embedded multi-tasked systems.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.
Proceedings of the 47th Design Automation Conference, 2010
2009
Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded Multiprocessing.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Temperature-aware register reallocation for register file power-density minimization.
ACM Trans. Design Autom. Electr. Syst., 2009
Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems.
ACM Trans. Embed. Comput. Syst., 2009
Low-power inter-core communication through cache partitioning in embedded multiprocessors.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Dynamic and application-driven I-cache partitioning for low-power embedded multitasking.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2008
Heterogeneously tagged caches for low-power embedded systems with virtual memory support.
ACM Trans. Design Autom. Electr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systems.
IET Comput. Digit. Tech., 2008
Compiler-driven register re-assignment for register file power-density and temperature reduction.
Proceedings of the 45th Design Automation Conference, 2008
Latency and bandwidth efficient communication through system customization for embedded multiprocessors.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
2007
Int. J. Parallel Program., 2007
The interval page table: virtual memory support in real-time and memory-constrained embedded systems.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems.
Proceedings of the 2007 International Conference on Compilers, 2007
2006
Low-power cache organization through selective tag translation for embedded processors with virtual memory support.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications.
Proceedings of the 43rd Design Automation Conference, 2006
2005
A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embed. Comput. Syst., 2005
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Energy-effcient physically tagged caches for embedded processors with virtual memory.
Proceedings of the 42nd Design Automation Conference, 2005
Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Application specific instruction memory transformations for power efficient, fault resilient embedded processors.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
2003
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Des. Test Comput., 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
Proceedings of the 2002 Design, 2002
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2001
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Data cache energy minimizations through programmable tag size matching to the applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
1991
IEEE Trans. Software Eng., 1991