Sobeeh Almukhaizim

According to our database1, Sobeeh Almukhaizim authored at least 37 papers between 2001 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2013
Predictive Techniques for Projecting Test Data Volume Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints.
J. Electron. Test., 2013

2011
Unified 2-D X-Alignment for Improving the Observability of Response Compactors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits.
J. Low Power Electron., 2011

Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits.
IET Comput. Digit. Tech., 2011

Analysis of the soft error susceptibility and failure rate in logic circuits.
Int. Arab J. Inf. Technol., 2011

Error-resilient design of branch predictors for effective yield improvement.
Proceedings of the 12th Latin American Test Workshop, 2011

2010
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power.
J. Electron. Test., 2010

Low-power test in compression-based reconfigurable scan architectures.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Predictive analysis for projecting test compression levels.
Proceedings of the 2011 IEEE International Test Conference, 2010

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG.
Proceedings of the 5th International Design and Test Workshop, 2010

Cost-free low-power test in compression-based reconfigurable scan designs.
Proceedings of the 5th International Design and Test Workshop, 2010

Reconfigurable low-power Concurrent Error Detection in logic circuits.
Proceedings of the 5th International Design and Test Workshop, 2010

Test power reduction in compression-based reconfigurable scan architectures.
Proceedings of the 15th European Test Symposium, 2010

2009
X-Align: Improving the Scan Cell Observability of Response Compactors.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

X-alignment techniques for improving the observability of response compactors.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires.
IEEE Trans. Reliab., 2008

Peak Power Reduction Through Dynamic Partitioning of Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Coping with Soft Errors in Asynchronous Burst-Mode Machines.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines.
IEEE Trans. Computers, 2007

2006
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Seamless Integration of SER in Rewiring-Based Design Space Exploration.
Proceedings of the 2006 IEEE International Test Conference, 2006

Berger code-based concurrent error detection in asynchronous burst-mode machines.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Compaction-based concurrent error detection for digital circuits.
Microelectron. J., 2005

Concurrent Error Detection in Asynchronous Burst-Mode Controllers.
Proceedings of the 2005 Design, 2005

2004
Cost-Driven Selection of Parity Trees.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Compiler-Based Frame Formation for Static Optimization.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

On Concurrent Error Detection with Bounded Latency in FSMs.
Proceedings of the 2004 Design, 2004

2003
On Compaction-Based Concurrent Error Detection.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2001
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001


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