Peter S. Colyer

According to our database1, Peter S. Colyer authored at least 2 papers between 1998 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

1998
The IBM JBIG-ABIC Verification Suite.
IBM J. Res. Dev., 1998


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