Philip H. Sweany

According to our database1, Philip H. Sweany authored at least 27 papers between 1987 and 2014.

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Bibliography

2014
Debugging teacher certification (abstract only).
Proceedings of the 45th ACM Technical Symposium on Computer Science Education, 2014

2008
FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field.
Journal of Systems Architecture - Embedded Systems Design, 2008

2007
Feasibility of decoupling memory management from the execution pipeline.
Journal of Systems Architecture, 2007

An FPGA implementation of elliptic curve cryptography for future secure web transaction.
Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007

2006
Tiny split data-caches make big performance impact for embedded applications.
J. Embedded Computing, 2006

A Study of Reconfigurable Split Data Caches and Instruction Caches.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

Speculative Thread Execution in a Multithreaded Dataflow Architecture.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
Improving data cache performance with integrated use of split caches, victim cache and stream buffers.
SIGARCH Computer Architecture News, 2005

2004
A Study of Separate Array and Scalar Caches.
Proceedings of the 18th Annual Symposium on High Performance Computing Systems and Applications, 2004

Automatic data partitioning for the agere payload plus network processor.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
An experimental evaluation of scalar replacement on scientific benchmarks.
Softw., Pract. Exper., 2003

2002
Loop fusion for clustered VLIW architectures.
Proceedings of the 2002 Joint Conference on Languages, 2002

Optimizing Loop Performance for Clustered VLIW Architectures.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Loop Transformations for Architectures with Partitioned Register Banks.
Proceedings of The Workshop on Languages, 2001

2000
Register Assignment for Software Pipelining with Partitioned Register Banks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Global Register Partitioning.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
Improving software pipelining with hardware support for self-spatial loads.
SIGARCH Computer Architecture News, 1999

1998
Building a Retargetable Local Instruction Scheduler.
Softw., Pract. Exper., 1998

Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies.
Digital Technical Journal, 1998

1997
Modulo Scheduling with Cache Reuse Information.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

1996
Improving Software Pipelining with Unroll-and-Jam.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

Extending List Scheduling to Consider Execution Frequency.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

1995
CRAIG: a practical framework for combining instruction scheduling and register assignment.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1992
Dominator-path scheduling: a global scheduling method.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1990
Post-compaction register assignment in a retargetable compiler.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1988
Horizon: A Retargetable Compiler for Horizontal Microarchitectures.
IEEE Trans. Software Eng., 1988

1987
Trace scheduling optimization in a retargetable microcode compiler.
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987


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