Philip K. F. Hölzenspies

According to our database1, Philip K. F. Hölzenspies authored at least 21 papers between 2003 and 2016.

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Bibliography

2016
A survey of offline algorithms for energy minimization under deadline constraints.
J. Sched., 2016

2015
Incremental Analysis of Cyclo-Static Synchronous Dataflow Graphs.
ACM Trans. Embed. Comput. Syst., 2015

Green Computing: Power Optimisation of VFI-Based Real-Time Multiprocessor Dataflow Applications.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Single-rate approximations of cyclo-static synchronous dataflow graphs.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Analytic Clock Frequency Selection for Global DVFS.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Multi-rate Equivalents of Cyclo-Static Synchronous Dataflow Graphs.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

Resource-Constrained Optimal Scheduling of Synchronous Dataflow Graphs via Timed Automata.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
Back to basics: Homogeneous representations of multi-rate synchronous dataflow graphs.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2011
Engineering Concurrent Software Guided by Statistical Performance Analysis.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

2010
On run-time exploitation of concurrency.
PhD thesis, 2010

Run-time Spatial Mapping of Streaming Applications to Heterogeneous Multi-Processor Systems.
Int. J. Parallel Program., 2010

Introducing the PilGRIM: A Processor for Executing Lazy Functional Languages.
Proceedings of the Implementation and Application of Functional Languages, 2010

An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Run-time spatial resource management for real-time applications on heterogeneous MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC).
Proceedings of the Design, Automation and Test in Europe, 2008

2007
The Chameleon Architecture for Streaming DSP Applications.
EURASIP J. Embed. Syst., 2007

Fast, Accurate and Detailed NoC Simulations.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Mapping streaming applications on a reconfigurable MPSoC platform at run-time.
Proceedings of the International Symposium on System-on-Chip, 2007

Using an FPGA for Fast Bit Accurate SoC Simulation.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Demonstration of Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC).
Proceedings of the Quantitative Aspects of Embedded Systems, 04.03. - 09.03.2007, 2007

2003
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003


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