Pascal T. Wolkotte

According to our database1, Pascal T. Wolkotte authored at least 18 papers between 2004 and 2010.

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Bibliography

2010
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
An Energy and Performance Exploration of Network-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP.
Int. J. Reconfigurable Comput., 2009

2008
Multi-core architectures and streaming applications.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

2007
The Chameleon Architecture for Streaming DSP Applications.
EURASIP J. Embed. Syst., 2007

Fast, Accurate and Detailed NoC Simulations.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Using an FPGA for Fast Bit Accurate SoC Simulation.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.
Proceedings of the FPL 2007, 2007

2006
A Virtual Channel Network-on-Chip for GT and BE traffic.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM.
Proceedings of the International Symposium on System-on-Chip, 2006

An optimal architecture for a DDC.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Efficient architectures for streaming applications.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Providing QoS Guarantees in a NoC by Virtual Channel Reservation.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Energy Model of Networks-on-Chip and a Bus.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Energy-Efficient NoC for Best-Effort Communication.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004


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