Philipp Schläfer

Affiliations:
  • Kaiserslautern University of Technology, Germany


According to our database1, Philipp Schläfer authored at least 11 papers between 2012 and 2017.

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Bibliography

2017
Implementation aspects of binary and non-binary low-density parity-check decoders = Implementierungsaspekte binärer und nicht-binärer Kanaldecodierer.
PhD thesis, 2017

2016
A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256).
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016

Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Error resilience and energy efficiency: An LDPC decoder design study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A new architecture for high throughput, low latency NB-LDPC check node processing.
Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

Syndrome based check node processing of high order NB-LDPC decoders.
Proceedings of the 22nd International Conference on Telecommunications, 2015

2013
A new dimension of parallelism in ultra high throughput LDPC decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Loopy - An open-source TCP/IP rapid prototyping and validation framework.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

ASIC implementation of a modified QR decomposition for tree search based MIMO detection.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012
Design Space of Flexible Multigigabit LDPC Decoders.
VLSI Design, 2012

FPGA-based rapid prototyping platform for MIMO-BICM design space exploration.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012


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