Ping Lu
Orcid: 0000-0002-0111-0573Affiliations:
- Lund University, Department of Electrical and Information Technology, Sweden
- Fudan University, Department of Microelectronics Engineering, Shanghai, China (PhD 2007)
According to our database1,
Ping Lu
authored at least 16 papers
between 2011 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
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on orcid.org
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Bibliography
2020
A Time-Domain 147fs<sub>rms 2.5</sub>-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2017
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise.
IEEE J. Solid State Circuits, 2017
2016
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
2014
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
A 1-1 MASH 2-D vernier time-to-digital converter with 2<sup>nd</sup>-order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps.
IEEE J. Solid State Circuits, 2012
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011