Pohua P. Chang

According to our database1, Pohua P. Chang authored at least 25 papers between 1988 and 1998.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1998
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1996
Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution.
Int. J. Parallel Program., 1996

Memory Optimizations in the Intel Reference Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Bidirectional Scheduling: A New Global Code Scheduling Approach.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

1995
Three Architecutral Models for Compiler-Controlled Speculative Execution.
IEEE Trans. Computers, 1995

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.
IEEE Trans. Computers, 1995

Integer Loop Code Generation for VLIW.
Proceedings of the Languages and Compilers for Parallel Computing, 1995

Profile-Guided Multi-Heuristic Branch Prediction.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

1994
Introduction.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
The superblock: An effective technique for VLIW and superscalar compilation.
J. Supercomput., 1993

The Effect of Code Expanding Optimizations on Instruction Cache Design.
IEEE Trans. Computers, 1993

1992
Efficient Instruction Sequencing with Inline Target Insertion.
IEEE Trans. Computers, 1992

Profile-guided Automatic Inline Expansion for C Programs.
Softw. Pract. Exp., 1992

Tolerating data access latency with register preloading.
Proceedings of the 6th international conference on Supercomputing, 1992

1991
Using Profile Information to Assist Classic Code Optimizations.
Softw. Pract. Exp., 1991

Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs.
Proceedings of the International Conference on Parallel Processing, 1991

1989
Inline Function Expansion for Compiling C Programs.
Proceedings of the ACM SIGPLAN'89 Conference on Programming Language Design and Implementation (PLDI), 1989

Comparing Software and Hardware Schemes For Reducing the Cost of Branches.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Achieving High Instruction Cache Performance with an Optimizing Compiler.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Control flow optimization for supercomputer scalar processing.
Proceedings of the 3rd international conference on Supercomputing, 1989

1988
Trace selection for compiling large C application programs to microcode.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988


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