Daniel M. Lavery

According to our database1, Daniel M. Lavery authored at least 20 papers between 1991 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Programming Spiking Neural Networks on Intel's Loihi.
Computer, 2018

2009
Performance Characterization of Itanium® 2-Based Montecito Processor.
Proceedings of the Computer Performance Evaluation and Benchmarking, 2009

2007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

2004
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2003
The compiler as a validation and evaluation tool.
Proceedings of the Compiler Optimization Meets Compiler Verification, 2003

Optimization for the Intel® Itanium ®Architectur Register Stack.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.
Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001
On the Importance of Points-to Analysis and Other Memory Disambiguation Methods for C Programs.
Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2001

Speculative precomputation: long-range prefetching of delinquent loads.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
An Advanced Optimizer for the IA-64 Architecture.
IEEE Micro, 2000

1997
Modulo Scheduling for Control-Intensive General-Purpose Programs
PhD thesis, 1997

1996
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.
IEEE Trans. Computers, 1995

Compiler technology for future microprocessors.
Proc. IEEE, 1995

Unrolling-based optimizations for modulo scheduling.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1993
The superblock: An effective technique for VLIW and superscalar compilation.
J. Supercomput., 1993

1992
Using Profile Information to Assist Advaced Compiler Optimization and Scheduling.
Proceedings of the Languages and Compilers for Parallel Computing, 1992

1991


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