Pradeep S. Nair

According to our database1, Pradeep S. Nair authored at least 11 papers between 2006 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors.
J. Low Power Electron., 2015

2012
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.
J. Low Power Electron., 2012

2011
Execution characteristics of embedded applications on a Pentium 4-based personal computer.
J. Embed. Comput., 2011

2009
Topology selection of FPGA look-up tables for low-leakage operation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006.
Proceedings of the 2009 International Conference on Computer Design, 2009

2008
Effects of Register File Organization on Leakage Power Consumption.
Proceedings of the 2008 International Conference on Computer Design, 2008

Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Analysing the performance of personal computers based on Intel microprocessors for sequence aligning bioinformatics applications.
Int. J. Bioinform. Res. Appl., 2007

Performance Analysis of an Intel Pentium-4 Based Personal Computer for Multiplke Sequence Alignment.
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
Performance Analysis of Embedded Applications on a Pentium-4 Based Machine.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006


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