Pradip A. Thaker

According to our database1, Pradip A. Thaker authored at least 5 papers between 1999 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2009
Holistic verification: myth or magic bullet?
Proceedings of the 46th Design Automation Conference, 2009

2003
A test evaluation technique for VLSI circuits using register-transfer level fault modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2000
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999


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