Minesh B. Amin
According to our database1, Minesh B. Amin authored at least 12 papers between 1992 and 2003.
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X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Efficient compression and application of deterministic patterns in a logic BIST architecture.
Proceedings of the 40th Design Automation Conference, 2003
Dynamic Scan: Driving Down the Cost of Test.
IEEE Computer, 2002
Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
A C3I Parallel Benchmark Based on Genetic Algorithms - Implementation and Performance Analysis.
J. Parallel Distrib. Comput., 1997
Workload Distribution in Fault Simulation.
J. Electronic Testing, 1997
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Zamlog: a parallel algorithm for fault simulation based on Zambezi.
Data parallel fault simulation.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
A Scalable Parallel Formulation of the Backpropagation Algorithm for Hypercubes and Related Architectures.
IEEE Trans. Parallel Distrib. Syst., 1994
An Adaptive, Load Balancing Parallel Join Algorithm.
Generalization by Neural Networks.
IEEE Trans. Knowl. Data Eng., 1992