Pradip Mandal

According to our database1, Pradip Mandal authored at least 67 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Ultra-low Power Current Comparator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020
Delta-sigma modulator based compact sensor signal acquisition front-end system.
Microelectron. J., 2020

Switched-Capacitor Common-Mode Feedback-Based Fully Differential Operational Amplifiers and its Usage in Implementation of Integrators.
J. Circuits Syst. Comput., 2020

Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects.
IET Circuits Devices Syst., 2020

2019
Fast locking, startup-circuit free, low area, 32-phase analog DLL.
Integr., 2019

Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Submanifolds of generalized \((k, \mu )\) -space-forms.
Period. Math. Hung., 2018

Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects.
IEEE J. Solid State Circuits, 2017

2016
A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
Spur reduction in frequency synthesizer with an array of switched capacitors.
Int. J. Circuit Theory Appl., 2015

High-speed energy-efficient bi-directional transceiver for on-chip global interconnects.
IET Circuits Devices Syst., 2015

Prediction of reference spur in frequency synthesisers.
IET Circuits Devices Syst., 2015

2014
ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing.
Integr., 2014

Spur reducing architecture of frequency synthesiser using switched capacitors.
IET Circuits Devices Syst., 2014

An approach to design and implementation of on-chip clock generator for the switched capacitor based embedded DC-DC converter.
Comput. Electr. Eng., 2014

2013
Modeling and design of CMOS analog circuits through hierarchical abstraction.
Integr., 2013

2012
A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter.
J. Low Power Electron., 2012

Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter.
J. Low Power Electron., 2012

Improvement of Power Efficiency and output voltage Ripple of Embedded DC-DC converters with Three Step Down ratios.
J. Circuits Syst. Comput., 2012

Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling.
Int. J. Circuit Theory Appl., 2012

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination.
Circuits Syst. Signal Process., 2012

A Fast Equation Free Iterative Approach to Analog Circuit Sizing.
Proceedings of the 25th International Conference on VLSI Design, 2012

Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Effcient approaches to overcome non-convexity issues in analog design automation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Spur suppression in frequency synthesizer using switched capacitor array.
Proceedings of the International SoC Design Conference, 2012

2011
Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect.
Microelectron. J., 2011

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications.
Microelectron. J., 2011

Technique for the reduction of output voltage ripple of switched capacitor-based DC??DC converters.
IET Circuits Devices Syst., 2011

A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A CAD methodology for automatic topology selection & sizing.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

An automated design methodology for yield aware analog circuit synthesis in submicron technology.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A geometric programming aided knowledge based approach for analog circuit synthesis and sizing.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Current-mode echo cancellation for full-duplex chip-to-chip data communication.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Switched-Capacitor Based Buck Converter Design Using Current Limiter.
J. Low Power Electron., 2009

Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

An automated design approach for CMOS LDO regulators.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing.
Proceedings of the ARTCom 2009, 2009

2008
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Integrated TIA-Equalizer for High Speed Optical Link.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
A Fractional Frequency Synthesizer Using Frequency Locked Loop.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
On-Chip Voltage Regulator with Improved Transient Response.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A single circuit solution for voltage sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High voltage tolerant output buffer design for mixed voltage interfaces.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Narrow Pulse- Suppressing Filter For Input Buffer.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001
CMOS op-amp sizing using a geometric programming formulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

1999
A New Approach for CMOS Op-Amp Synthesis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1997
A Self-Biased High Performance Folded Cascode CMOS Op-Amp.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Design of high performance two stage CMOS cascode op-amps with stable biasing.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1993
Macromodeling of the A.C. characteristics of CMOS Op-amps.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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