Vijaya Sankara Rao Pasupureddi
Orcid: 0000-0003-2860-4749
According to our database1,
Vijaya Sankara Rao Pasupureddi
authored at least 42 papers
between 2008 and 2024.
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Bibliography
2024
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
2023
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.
Int. J. Circuit Theory Appl., August, 2023
0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2023
2022
A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects.
Int. J. Circuit Theory Appl., December, 2022
Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 2<sup>7</sup>-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS.
Circuits Syst. Signal Process., 2021
A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects.
Microelectron. J., 2020
Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS.
Int. J. Circuit Theory Appl., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A -40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization.
Int. J. Circuit Theory Appl., 2019
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2018
Elektrotech. Informationstechnik, 2018
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2016
IEEE Trans. Aerosp. Electron. Syst., 2016
Microelectron. J., 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
A low-power area-efficient compressive sensing approach for multi-channel neural recording.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling.
Int. J. Circuit Theory Appl., 2012
A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination.
Circuits Syst. Signal Process., 2012
2011
Microelectron. J., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
2010
A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2008
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008