Prasad R. Chalasani

According to our database1, Prasad R. Chalasani authored at least 5 papers between 1989 and 1995.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1995
Parallel computing for network optimization: a cluster-based approach for the dual transshipment problem.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

1994
Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm.
Proceedings of the International Symposium on Parallel Architectures, 1994

1993
Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Parallel Network Dual Simplex Method on a Shared Memory Multiprocessor.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

1989
Design of Testable VLSI Circuits with Minumum Area Overhead.
IEEE Trans. Computers, 1989


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