Sudipta Bhawmik

According to our database, Sudipta Bhawmik authored at least 30 papers between 1988 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

ACM Trans. Design Autom. Electr. Syst., 2015

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

At-speed interconnect testing and test-path optimization for 2.5D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Built-in self-test for interposer-based 2.5D ICs.

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Impact of mid-bond testing in 3D stacked ICs.

Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Using 3D-COSTAR for 2.5D test cost optimization.

Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2003

The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.

Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.

Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik

J. Electron. Test., 2002

Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch.

Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Introduction to SystemC.

Sudipta Bhawmik

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

On improving test quality of scan-based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A BIST scheme for RTL circuits based on symbolic testabilityanalysis.

Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Core Based ASIC Design.

Frank P. Higgins, Sudipta Bhawmik

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing.

Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme.

Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik

Proceedings of the 36th Conference on Design Automation, 1999

1998

Efficient test-point selection for scan-based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik

IEEE Trans. Very Large Scale Integr. Syst., 1998

An almost full-scan BIST solution-higher fault coverage and shorter test application time.

Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A BIST scheme for the detection of path-delay faults.

Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis.

Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik

Proceedings of the 35th Conference on Design Automation, 1998

1997

A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.

Sudipta Bhawmik, Indradeep Ghosh

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik

Proceedings of the 34st Conference on Design Automation, 1997

1995

Integration of partial scan and built-in self-test.

Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik

J. Electron. Test., 1995

1993

PSBIST: A Partial-Scan Based Built-In Self-Test Scheme.

Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1991

Enhanced Controllability for <i>I_DDQ</i> Test Sets Using Partial Scan.

Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin

Proceedings of the 28th Design Automation Conference, 1991

1989

Design of Testable VLSI Circuits with Minumum Area Overhead.

Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, Parimal Palchaudhuri

IEEE Trans. Computers, 1989

Expert system to configure global design for testability structure in a VLSI circuit.

Sudipta Bhawmik, Parimal Pal Chaudhuri

Microprocess. Microsystems, 1989

KIDLAN: A hardware description language.

Anurag Acharya, Sudipta Bhawmik, C. R. K. Prasad, Parimal Palchaudhuri

Microprocessing and Microprogramming, 1989

Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach.

Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri

Integr., 1989

DFT Expert: designing testable VLSI circuits.

Sudipta Bhawmik, Parimal Palchaudhuri

IEEE Des. Test, 1989

1988

DFTEXPERT: An Expert System for Design of Testable VLSI Circuits.

Sudipta Bhawmik, Parimal Pal Chaudhuri

Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1988, June 1-3, 1988, Tullahoma, TN, USA. ACM, 1988, 1988