Puneet Sabbarwal

According to our database, Puneet Sabbarwal authored at least 3 papers in 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation.

Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management.

Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji

Proceedings of the 2011 IEEE International Test Conference, 2011

Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system.

Lakshmanan Balasubramanian, Puneet Sabbarwal, Rajesh Kumar Mittal, Prakash Narayanan, Ranjit Kumar Dash, Anand Devendra Kudari, Srikanth Manian, Sudhir Polarouthu, Harikrishna Parthasarathy, Ravi C. Vijayaraghavan, Sachin Turkewadikar

Proceedings of the Design, Automation and Test in Europe, 2011