Purandar Bhaduri

Orcid: 0000-0002-8847-0394

Affiliations:
  • IIT Guwahati, India


According to our database1, Purandar Bhaduri authored at least 34 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Coalgebras for Bisimulation of Weighted Automata over Semirings.
Log. Methods Comput. Sci., 2023

2020
An energy-efficient time-triggered scheduling algorithm for mixed-criticality systems.
Des. Autom. Embed. Syst., 2020

2019
Translation Validation of Code Motion Transformations Involving Loops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Counter-example generation procedure for path-based equivalence checkers.
IET Softw., 2019

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Formal Verification of Optimizing Transformations during High-level Synthesis.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2018
On the structure of C-algebras through atomicity and if-then-else.
CoRR, 2018

Time-Triggered Scheduling for Multiprocessor Mixed-Criticality Systems.
Proceedings of the Distributed Computing and Internet Technology, 2018

2017
Time-Triggered Scheduling of Mixed-Criticality Systems.
ACM Trans. Design Autom. Electr. Syst., 2017

Axiomatization of if-then-else over possibly non-halting programs and tests.
Int. J. Algebra Comput., 2017

Axiomatization of if-then-else over monoids of possibly non-halting programs and tests.
CoRR, 2017

Translation Validation of Loop Invariant Code Optimizations Involving False Computations.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015
Performance Modeling and Analysis of IEEE 802.11 IBSS PSM in Different Traffic Conditions.
IEEE Trans. Mob. Comput., 2015

Reconfigurable Communication Middleware for Flex Ray-Based Distributed Embedded Systems.
Proceedings of the 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2015

2014
Probabilistic model checking of IEEE 802.11 IBSS power save mode.
Int. J. Wirel. Mob. Comput., 2014

Performance modeling and evaluation of IEEE 802.11 IBSS power save mode.
Ad Hoc Networks, 2014

Virtual Integration of Real-Time Systems Based on Resource Segregation Abstraction.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2014

2013
Real-time scheduling interfaces and contracts for the design of distributed embedded systems.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Characterizing feedback signal drop patterns in formal verification of networked control systems.
Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013

2012
Performance analysis of IEEE 802.11 IBSS power save mode using a discrete-time markov model.
Proceedings of the ACM Symposium on Applied Computing, 2012

2010
Performance analysis of FlexRay-based systems using real-time calculus, revisited.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

A proposal for real-time interfaces in SPEEDS.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
Interface synthesis and protocol conversion.
Formal Aspects Comput., 2008

Modeling Fixed Priority Non-Preemptive Scheduling with Real-Time Calculus.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

2006
Verification of Giotto based Embedded Control Systems.
Nord. J. Comput., 2006

Synthesis of Synchronous Interfaces.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Synthesis of Interface Automata.
Proceedings of the Automated Technology for Verification and Analysis, 2005

2004
Model Checking of Statechart Models: Survey and Research Directions
CoRR, 2004

2003
Verification of Scenario-based Specifications using Templates.
Proceedings of the International Workshop on Software Verification and Validation, 2003

Model Checking Visual Specification of Requirements.
Proceedings of the 1st International Conference on Software Engineering and Formal Methods (SEFM 2003), 2003

2002
Formal Techniques for Analysing Scenarios using Message Sequence Charts.
Proceedings of the Validation and Implementation of Scenario-based Specifications, 2002

2001
Formalizing Models and Meta-models for System Development.
Proceedings of the 8th Asia-Pacific Software Engineering Conference (APSEC 2001), 2001

1999
An Application of Compiler Technology to the Year 2000 Problem.
Softw. Pract. Exp., 1999

Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999


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