Qingwen Wei

Orcid: 0009-0009-7047-7182

According to our database1, Qingwen Wei authored at least 9 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model.
CoRR, 2024

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs.
Proceedings of the International Conference on Compilers, 2023


  Loading...