Xilong Kang
Orcid: 0009-0002-3853-2398
According to our database1,
Xilong Kang authored at least 7 papers
between 2025 and 2026.
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Bibliography
2026
Low Bit-Width LLM Acceleration via Symmetric Lookup Format and Compute-in-Decoding Paradigm.
IEEE Trans. Computers, July, 2026
A 51.6μJ/Token Subspace-Rotation-Based Dual-Quantized Large-language-Model Accelerator with Fused Scale-Activation INT Datapath and Rearranged Bit-Slice LUT Computation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
3D-TANoC: Thermal-Aware 3D LLM Accelerator with Hierarchical NoC and Operator-Aware Dataflow Mapping Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025
A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025