Quentin Diduck

According to our database1, Quentin Diduck authored at least 9 papers between 2003 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
Minimization of maximum electric field in high-voltage parallel-plate capacitor.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016

2012
Measurement of thermal boundary resistance in AlGaN/GaN HEMTs using Liquid Crystal Thermography.
Proceedings of the 2012 Proceedings of the 35th International Convention, 2012

2009
Ballistic Deflection Transistors and the Emerging Nanoscale Era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Study of leakage current mechanisms in ballistic deflection transistors.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2006
Process tolerant calibration circuit for PLL applications with BIST.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A New Test Methodology For DNL Error In Flash ADC's.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
6-bit low power low area frequency modulation based flash ADC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters.
Proceedings of the IFIP VLSI-SoC 2003, 2003

1.8V 0.18µm CMOS Novel Successive Approximation ADC.
Proceedings of the IFIP VLSI-SoC 2003, 2003


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