Martin Margala

According to our database1, Martin Margala authored at least 136 papers between 1994 and 2019.

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2019
Evolutionary Cell Aided Design for Neural Network Architectures.
CoRR, 2019

Echo Detection Using Differentiation for Compact LIDAR Implementation.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

2018
A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System.
IEEE Trans. on Circuits and Systems, 2018

5-Gb/s linear re-driver in 180 nm CMOS technology.
Microelectron. J., 2018

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators.
J. Electronic Testing, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs.
CoRR, 2018

THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Terahertz travelling wave amplifier design using Ballistic Deflection Transistor.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A droop measurement built-in self-test circuit for digital low-dropout regulators.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.
J. Signal Process. Syst., 2017

ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration.
Proceedings of the New Generation of CAS, 2017

Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A high performance Full Adder based on Ballistic Deflection Transistor technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Column-wise ROIC design with on-chip calibration for photoresistive image sensor.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A CMOS Ripple Detector for Voltage Regulator Testing.
J. Electronic Testing, 2016

A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems.
CoRR, 2016

Document classification systems in heterogeneous computing environments.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

A new level sensitive D Latch using Ballistic nanodevices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters.
CoRR, 2015

A CMOS ripple detector for integrated voltage regulator testing.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Aparapi-UCores: A high level programming framework for unconventional cores.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015

A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
High Level Programming for Heterogeneous Architectures.
CoRR, 2014

Low power RAM-based hierarchical CAM on FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Modified fused multiply-accumulate chained unit.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

High level programming of FPGAs for HPC and data centric applications.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

A novel low-power and in-place split-radix FFT processor.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

High level programming framework for FPGAs in the data center.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA implementation of low-power split-radix FFT processors.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification.
SIGARCH Computer Architecture News, 2013

An IDDQ BIST approach to characterize phase-locked loop parameters.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An FPGA memcached appliance.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

High throughput filtering using FPGA-acceleration.
Proceedings of the 22nd ACM International Conference on Information and Knowledge Management, 2013

2012
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application.
Int. J. Reconfigurable Comput., 2012

Novel Practical Built-in Current Sensors.
J. Electronic Testing, 2012

Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability.
J. Electronic Testing, 2012

Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Evaluating FPGA-acceleration for real-time unstructured search.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

2011
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.
J. Low Power Electron., 2010

Radiation-Hardened Reconfigurable Array With Instruction Roll-Back.
Embedded Systems Letters, 2010

Power minimization methodology for VCTL topologies.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

An area efficient design methodology for SEU tolerant digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of self correcting radiation hardened digital circuits using decoupled ground bus.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Topology impact on the room temperature performance of THz-range ballistic deflection transistors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A new built-in IDDQ testing method using programmable BICS.
Proceedings of the 15th European Test Symposium, 2010

A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

2009
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Ballistic Deflection Transistors and the Emerging Nanoscale Era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

New performance/power/area efficient, reliable full adder design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Varicap threshold logic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Study of leakage current mechanisms in ballistic deflection transistors.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A portless SRAM Cell using stunted wordline drivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Digital BIST for Phase-Locked Loops.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
A Processor-In-Memory Architecture for Multimedia Compression.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Portless SRAM - A High-Performance Alternative to the 6T Methodology.
J. Solid-State Circuits, 2007

A Self-Biased Charge-Transfer Sense Amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Process and Temperature Calibration of PLLs with BiST Capabilities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A versatile computation module for adaptable multimedia processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Process tolerant calibration circuit for PLL applications with BIST.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An integrated countermeasure against differential power analysis for secure smart-cards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

New Embedded Core Testing for System-on-Chips and System-in-Packages.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Adaptable Architectures for Signal Processing Applications.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Design of wireless on-wafer submicron characterization system.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Defect detection in analog and mixed circuits by neural networks using wavelet analysis.
IEEE Trans. Reliability, 2005

Efficient Addition Circuits for Modular Design of Processors-in-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A current based self-test methodology for RF front-end circuits.
Microelectron. J., 2005

A novel five-transistor (5T) sram cell for high performance cache.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A new SoC test architecture with RF/wireless connectivity.
Proceedings of the 10th European Test Symposium, 2005

A New Test Methodology For DNL Error In Flash ADC's.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
New approach to design for reusability of arithmetic cores in systems-on-chip.
Integr., 2004

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.
J. Electronic Testing, 2004

Design of Wireless Sub-Micron Characterization System.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Cost Model Analysis of DFT Based Fault Tolerant SOC Designs.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Sobel edge detection processor for a real-time volume rendering system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

6-bit low power low area frequency modulation based flash ADC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A versatile built-in CMOS sensing device for digital circuit parametric test.
IEEE Trans. Instrumentation and Measurement, 2003

Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters.
Proceedings of the IFIP VLSI-SoC 2003, 2003

1-V ADPCM Processor for Low-Power Wireless Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003

1.8V 0.18µm CMOS Novel Successive Approximation ADC.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Control Constrained Resource Partitioning for Complex SoCs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Low-voltage analog current detector supporting at-speed BIST.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Minimizing concurrent test time in SoC's by balancing resource usage.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Neural Networks-Based Parametric Testing of Analog IC.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Fast and low-power inner product processor.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.
Proceedings of the SOC Design Methodologies, 2001

2000
I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999
Low-Power Memory Circuits.
Proceedings of the VLSI Handbook., 1999

Low-Power SRAM Circuit Design.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Low Power SRAMs for Battery Operation.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

1995
A 33 MHz 16-bit gradient calculator for real-time volume imaging.
Comput. Graph., 1995

1994
A 33MHz 16. Bit Gradient Calculator for Real-Time Volume Imaging.
Proceedings of the EGGH94: Eurographics Workshop on Graphics Hardware 1994, 1994


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