Martin Margala
Orcid: 0000-0002-0034-0369Affiliations:
- University of Louisiana at Lafayette, LA, USA
- University of Massachusetts Lowell, USA (former)
- University of Rochester, New York, USA (former)
According to our database1,
Martin Margala
authored at least 158 papers
between 1994 and 2024.
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Bibliography
2024
Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing.
IEEE Access, 2024
2023
Fault-Tolerant Trust-Based Task Scheduling Algorithm Using Harris Hawks Optimization in Cloud Computing.
Sensors, September, 2023
Prioritized Task-Scheduling Algorithm in Cloud Computing Using Cat Swarm Optimization.
Sensors, July, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Optimum Supply Voltage for High Gain Amplifier in Telemetry Circuitry for Ultra-Low Power Implantable Cardiac Pacemaker.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search.
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators.
J. Electron. Test., 2018
CoRR, 2018
THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
2017
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.
J. Signal Process. Syst., 2017
Proceedings of the New Generation of CAS, 2017
Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems.
CoRR, 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
CoRR, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015
A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification.
SIGARCH Comput. Archit. News, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the 22nd ACM International Conference on Information and Knowledge Management, 2013
2012
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application.
Int. J. Reconfigurable Comput., 2012
J. Electron. Test., 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012
2011
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
J. Low Power Electron., 2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Design of self correcting radiation hardened digital circuits using decoupled ground bus.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Topology impact on the room temperature performance of THz-range ballistic deflection transistors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 15th European Test Symposium, 2010
A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010
2009
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
An integrated countermeasure against differential power analysis for secure smart-cards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Defect detection in analog and mixed circuits by neural networks using wavelet analysis.
IEEE Trans. Reliab., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Microelectron. J., 2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
Integr., 2004
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Sobel edge detection processor for a real-time volume rendering system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
6-bit low power low area frequency modulation based flash ADC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Instrum. Meas., 2003
Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters.
Proceedings of the IFIP VLSI-SoC 2003, 2003
1-V ADPCM Processor for Low-Power Wireless Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003
1.8V 0.18µm CMOS Novel Successive Approximation ADC.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Application-specific low-voltage current amplifier for system-on-chip I<sub>DDQ</sub> test.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.
Proceedings of the SOC Design Methodologies, 2001
A novel wide-band CMOS current amplifying cell and its application in power supply current monitoring.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
1999
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999
1998
Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study.
IEEE J. Solid State Circuits, 1998
1995
Comput. Graph., 1995
1994
Proceedings of the EGGH94: Eurographics Workshop on Graphics Hardware 1994, 1994