R. Castagnetti

According to our database1, R. Castagnetti authored at least 5 papers between 2001 and 2009.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2006
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2001
Substrate Engineering to Improve Soft-Error-Rate Immunity for SRAM Technologies.
Microelectron. Reliab., 2001


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