Ramakrishnan Venkatraman

According to our database1, Ramakrishnan Venkatraman authored at least 19 papers between 2000 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Dynamic Co-Simulation Methods for Combined Transmission-Distribution System and Integration Time Step Impact on Convergence.
CoRR, 2018

2012
A Silicon Testing Strategy for Pulse-Width Failures.
Proceedings of the 25th International Conference on VLSI Design, 2012

Placement aware clock gate cloning and redistribution methodology.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Ensuring On-Die Power Supply Robustness in High-Performance Designs.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

DFM: Impact analysis in a high performance design.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2009
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimization strategies to improve statistical timing.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Early clock prototyping for design analysis and quality entitlement.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2006
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
A Soft-Switched Full-Bridge Single-Stage AC-to-DC Converter With Low-Line-Current Harmonic Distortion.
IEEE Trans. Ind. Electron., 2005

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2000
Soft-switching single-stage AC-to-DC converter with low harmonic distortion.
IEEE Trans. Aerosp. Electron. Syst., 2000

Rule-based system application for a technical problem in inventory issue.
Artif. Intell. Eng., 2000

An evolutionary approach to timing driven FPGA placement.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000


  Loading...