Ramakrishnan Venkatraman

According to our database, Ramakrishnan Venkatraman authored at least 29 papers between 1994 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2026

Aging-Aware Timing Models for Reliability Enhancement of Inverter-Transmission Gate-Based Circuits.

Neha Gupta, Lomash Chandra Acharya, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, Arvind Kumar Sharma, Ajoy Mandal, Ramakrishnan Venkatraman, Sudeb Dasgupta, Anand Bulusu

IEEE Des. Test, June, 2026

2025

LiMo: A Framework Leveraging Machine Learning for Multi-Input Switching Timing Models of Complex Logic Gates.

Pooja Beniwal, Sneh Saurabh, N. Vignesh Chowdary, Suriya Skariah, Ajoy Mandal, Ramakrishnan Venkatraman

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025

Adaptive fabrication of material extrusion-AM process using machine learning algorithms for print process optimization.

S. Sridhar, K. Venkatesh, G. Revathy, M. Venkatesan, R. Venkatraman

J. Intell. Manuf., October, 2025

Gateways for Institutional-Grade Commerce and Interoperability of Digital Assets.

Rafael Belchior, Thomas Hardjono, Alexandru Chiriac, Ramakrishnan Venkatraman

CoRR, January, 2025

2024

Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis.

Lomash Chandra Acharya, Arvind K. Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Neha Gupta, Nayakanti Sai Shabarish, Ajoy Mandal, Ramakrishnan Venkatraman, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

2023

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Ramakrishnan Venkatraman, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.

Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Ramakrishnan Venkatraman, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 19th International Conference on Synthesis, 2023

Accurate Representation of Distribution System Dynamics in Bulk System Studies by Clusters of Composite Load Models.

Amarsagar Reddy Ramapuram Matavalam, R. Venkatraman, Venkataramana Ajjarapu

Proceedings of the IEEE Industry Applications Society Annual Meeting, 2023

2021

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.

Lomash Chandra Acharya, Arvind Kumar Sharma, Ramakrishnan Venkatraman, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2018

Dynamic Co-Simulation Methods for Combined Transmission-Distribution System and Integration Time Step Impact on Convergence.

Ramakrishnan Venkatraman, Siddhartha Kumar Khaitan, Venkataramana Ajjarapu

CoRR, 2018

2012

A Silicon Testing Strategy for Pulse-Width Failures.

Srinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman

Proceedings of the 25th International Conference on VLSI Design, 2012

Placement aware clock gate cloning and redistribution methodology.

Ramamurthy Vishweshwara, Mahita Nagabhiru, Ramakrishnan Venkatraman

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Ensuring On-Die Power Supply Robustness in High-Performance Designs.

Sreekanth Soman, Amit Brahme, Ramakrishnan Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

DFM: Impact analysis in a high performance design.

S. M. Stalin, Amit Brahme, Ramakrishnan Venkatraman, Ajoy Mandal

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2009

An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.

Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.

R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimization strategies to improve statistical timing.

Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Early clock prototyping for design analysis and quality entitlement.

Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.

R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2006

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.

R. Venkatraman, R. Castagnetti, S. Ramesh

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.

Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

A Soft-Switched Full-Bridge Single-Stage AC-to-DC Converter With Low-Line-Current Harmonic Distortion.

Ashoka K. S. Bhat, Ramakrishnan Venkatraman

IEEE Trans. Ind. Electron., 2005

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.

Ruggero Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.

F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.

Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

Soft-switching single-stage AC-to-DC converter with low harmonic distortion.

Ramakrishnan Venkatraman, Ashoka K. S. Bhat, Mark Edmunds

IEEE Trans. Aerosp. Electron. Syst., 2000

Rule-based system application for a technical problem in inventory issue.

R. Venkatraman, S. Venkatraman

Artif. Intell. Eng., 2000

An evolutionary approach to timing driven FPGA placement.

R. Venkatraman, Lalit M. Patnaik

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1994

Common Ada bindings to compartmented mode workstations.

C. Armstrong, R. Venkatraman

Proceedings of the Eleventh Annual Washington Ada Symposium & summer ACM SIGAda Meeting on Ada, 1994