R. V. Jawalekar

According to our database1, R. V. Jawalekar authored at least 2 papers between 1994 and 1995.

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Bibliography

1995
AVPGEN-A test generator for architecture verification.
IEEE Trans. Very Large Scale Integr. Syst., 1995

1994
Architectural Verification of Processors Using Symbolic Instruction Graphs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994


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