Indira Nair

According to our database1, Indira Nair authored at least 18 papers between 1986 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory.
IBM Journal of Research and Development, 2013

2012
Power management of multi-core chips: Challenges and pitfalls.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010
The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise.
J. Low Power Electronics, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Power Management and Its Impact on Power Supply Noise.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
Exploring power management in multi-core systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.
Design Autom. for Emb. Sys., 2005

2004
An efficient system-on-a-chip design methodology for networking applications.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
SEAS: a system for early analysis of SoCs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Early analysis tools for system-on-a-chip design.
IBM Journal of Research and Development, 2002

1997
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system.
IEEE Trans. VLSI Syst., 1997

1995
AVPGEN-A test generator for architecture verification.
IEEE Trans. VLSI Syst., 1995

1994
Architectural Verification of Processors Using Symbolic Instruction Graphs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992
A Small Test Generator for Large Designs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Symbolic implication in test generation.
Proceedings of the conference on European design automation, 1991

1986
Evaluating an information system for policy modeling and uncertainty analysis.
JASIS, 1986

Efficient Fault Simulation of CMOS Circuits with Accurate Models.
Proceedings of the Proceedings International Test Conference 1986, 1986


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