Raghava Katreepalli

According to our database, Raghava Katreepalli authored at least 3 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of four.

2019

Power efficient synchronous counter design.

Raghava Katreepalli, Themistoklis Haniotakis

Comput. Electr. Eng., 2019

2017

High Speed Power Efficient Carry Select Adder Design.

Raghava Katreepalli, Themistoklis Haniotakis

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design.

Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016