Yiorgos Tsiatouhas

According to our database, Yiorgos Tsiatouhas authored at least 102 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems.

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the International Conference on Artificial Intelligence in Information and Communication , 2024

2023

An aging monitoring scheme for SRAM decoders.

Helen-Maria Dounavi, Yiorgos Tsiatouhas

Integr., 2023

Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain.

Vasileios Tenentes, Athanasios Xynos, Christos Zonios, Asimina Koutra, Christina Dilopoulou, Konstantinos Tsampiras, Yiorgos Tsiatouhas, Daniele Rossi

Proceedings of the 8th South-East Europe Design Automation, 2023

BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs.

Christina Dilopoulou, Yiorgos Tsiatouhas

Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation.

Christina Dilopoulou, Yiorgos Tsiatouhas

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs.

Athanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas

Proceedings of the IEEE European Test Symposium, 2023

2022

Efficient Dynamic Logic Magnitude Comparators.

Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

BTI Aging Influence on Charge Pump Circuits.

Spyridon Spyridonos, Yiorgos Tsiatouhas

Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles.

Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the 10th IEEE International Black Sea Conference on Communications and Networking, 2022

2021

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs.

Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos

J. Electron. Test., 2021

Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier.

Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas

J. Electron. Test., 2021

An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems.

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas

Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2021

2020

An Alternative Post-bond Testing Method for TSVs.

Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Monitoring of BTI and HCI Aging in SRAM Decoders.

Helen-Maria Dounavi, Yiorgos Tsiatouhas

Proceedings of the IEEE European Test Symposium, 2020

2019

On the Static CMOS Implementation of Magnitude Comparators.

Costas Efstathiou, Yiorgos Tsiatouhas

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2018

Aging monitoring in SRAM sense amplifiers.

Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Periodic Aging Monitoring in SRAM Sense Amplifiers.

Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Low Power and High Speed Static CMOS Digital Magnitude Comparators.

Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs.

Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

BTI and HCI degradation detection in SRAM cells.

Yiorgos Sfikas, Yiorgos Tsiatouhas

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Variation tolerant BTI monitoring in SRAM cells.

Yiorgos Sfikas, Yiorgos Tsiatouhas

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Periodic Bias-Temperature Instability monitoring in SRAM cells.

Yiorgos Tsiatouhas

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Timing Error Tolerance in Small Core Designs for SoC Applications.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

IEEE Trans. Computers, 2016

Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs.

Yiorgos Sfikas, Yiorgos Tsiatouhas

IEEE Trans. Computers, 2016

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design.

Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Timing error mitigation in microprocessor cores.

Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

A current monitoring technique for I_DDQ testing in digital integrated circuits.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Integr., 2015

Scan chain based at-speed diagnosis in the presence of scan output compaction schemes.

Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

On the reuse of existing error tolerance circuitry for low power scan testing.

Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Soft error immune latch under SEU related double-node charge collection.

Katerina Katsarou, Yiorgos Tsiatouhas

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

On resistive open defect detection in DRAMs: The charge accumulation effect.

Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui

Proceedings of the 20th IEEE European Test Symposium, 2015

Fast deployment of alternate analog test using Bayesian model fusion.

John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A method for the estimation of defect detection probability of analog/RF defect-oriented tests.

John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas

IEEE Trans. Very Large Scale Integr. Syst., 2014

Layout-Based Refined NPSF Model for DRAM Characterization and Testing.

Yiorgos Sfikas, Yiorgos Tsiatouhas, Said Hamdioui

IEEE Trans. Very Large Scale Integr. Syst., 2014

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches.

Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

The Time Dilation Technique for Timing Error Tolerance.

Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos

IEEE Trans. Computers, 2014

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique.

Efi Arvaniti, Yiorgos Tsiatouhas

J. Electron. Test., 2014

Double node charge sharing SEU tolerant latch design.

Katerina Katsarou, Yiorgos Tsiatouhas

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Power efficient scan testing by exploiting existing error tolerance circuitry in a design.

Anthi Anastasiou, Yiorgos Tsiatouhas

Proceedings of the 19th IEEE European Test Symposium, 2014

Stuck-at fault diagnosis in scan chains.

Helen-Maria Dounavi, Yiorgos Tsiatouhas

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers.

John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas

IEEE Trans. Instrum. Meas., 2013

New High-Speed Multioutput Carry Look-Ahead Adders.

Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables.

John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Effective Timing Error Tolerance in Flip-Flop Based Core Designs.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos

J. Electron. Test., 2013

NBTI aging tolerance in pipeline based designs NBTI.

Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques.

Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

The leafs scan-chain for test application time and scan power reduction.

Maria Chalkia, Yiorgos Tsiatouhas

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 17th IEEE European Test Symposium, 2012

A novel architecture to reduce test time in march-based SRAM tests.

Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Single event upset tolerance in flip-flop based microprocessor cores.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Low power scan by partitioning and scan hold.

Efi Arvaniti, Yiorgos Tsiatouhas

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

A Robust and Reconfigurable Multi-mode Power Gating Architecture.

Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A BIST scheme for testing and repair of multi-mode power switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

Proceedings of the 16th European Test Symposium, 2011

2010

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers.

Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Receiver Circuit for Low-Swing Interconnect Schemes.

Yiannis Moisiadis, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Memory-Less Pipeline Dynamic Circuit Design Technique.

Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Timing error tolerance in nanometer ICs.

Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

A Build-In Self-Test technique for RF Mixers.

Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing.

Yiorgos Sfikas, Yiorgos Tsiatouhas

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A Current Mode, Parallel, Two-Rail Code Checker.

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni

IEEE Trans. Computers, 2008

Timing Error Detection and Correction by Time Dilation.

Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

2007

Testable Designs of Multiple Precharged Domino Circuits.

Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

IEEE Trans. Very Large Scale Integr. Syst., 2007

A Stress-Relaxed Negative Voltage-Level Converter.

Yiorgos Tsiatouhas

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Scan Flip-Flop for Low-Power Scan Operation.

Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias

Proceedings of the 14th IEEE International Conference on Electronics, 2007

An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers.

Lampros Dermentzoglou, Anastasios Karagounis, Aggeliki Arapoyanni, Yiorgos Tsiatouhas

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

A Design Technique for Energy Reduction in NORA CMOS Logic.

Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

High fan-in differential current mirror logic.

Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism.

Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

The Use of Pre-Evaluation Phase in Dynamic CMOS Logic.

A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Built-In Self-Test Scheme for Differential Ring Oscillators.

Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Fast, Parallel Two-Rail Code Checker with Enhanced Testability.

Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

An embedded IDDQ testing circuit and technique.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 12th IEEE International Conference on Electronics, 2005

A built-in I_DDQ testing circuit.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs.

Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

J. Electron. Test., 2004

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators.

Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni

J. Electron. Test., 2004

Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications .

Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.

A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003

An Embedded IDDQ Testing Architecture and Technique.

Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs.

Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A low power NORA circuit design technique based on charge recycling.

Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A novel scheme for testing radio frequency voltage controlled oscillators.

Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002

A new technique for IDDQ testing in nanometer technologies.

Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni

Integr., 2002

Extending the Viability of IDDQ Testing in the Deep Submicron Era.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology.

A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing.

Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

Concurrent Detection of Soft Errors Based on Current Monitoring.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A new flash memory sense amplifier in 0.18 μm CMOS technology.

A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

New test pattern generation units for NPSF oriented memory built-in self test.

A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Management of charge pump circuits.

George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni

Integr., 2000

On Testability of Multiple Precharged Domino Logic.

Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A Compact Built-In Current Sensor for IDDQ Testing.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

New memory sense amplifier designs in CMOS technology.

Y. Tsiatouhas, A. Chrisanthopoulos, George Kamoulakos, Th. Haniotakis

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A state assignment algorithm for finite state machines.

Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A test pattern generation unit for memory NPSF built-in self test.

A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A Versatile Built-In Self-Test Scheme for Delay Fault Testing.

Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos

Proceedings of the 2000 Design, 2000

1999

Novel domino logic designs.

Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

On Path Delay Fault Testing of Multiplexer - Based Shifters.

Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing.

Y. Tsiatouhas, Th. Haniotakis

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.

Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas

Proceedings of the 1999 Design, 1999

1998

C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.

Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998