Rakesh Warrier

According to our database, Rakesh Warrier authored at least 5 papers between 2014 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures.

Rakesh Warrier, Wei Zhang, Chan Hua Vun

Circuits Syst. Signal Process., 2017

Fracturable DSP Block for Multi-context Reconfigurable Architectures.

Rakesh Warrier, Shanker Shreejith, Wei Zhang, Chan Hua Vun, Suhaib A. Fahmy

Circuits Syst. Signal Process., 2017

2015

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.

Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Reconfigurable DSP block design for dynamically reconfigurable architecture.

Rakesh Warrier, Hao Liang, Wei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low-power pipelined MAC architecture using Baugh-Wooley based multiplier.

Rakesh Warrier, Chan Hua Vun, Wei Zhang

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014