Suhaib A. Fahmy

Orcid: 0000-0003-0568-5048

Affiliations:
  • King Abdullah University of Science and Technology, Saudi Arabia
  • University of Warwick, United Kingdom (former)
  • Nanyang Technological University, Singapore (former)


According to our database1, Suhaib A. Fahmy authored at least 137 papers between 2005 and 2024.

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Bibliography

2024
Collaborative Learning at the Edge for Air Pollution Prediction.
IEEE Trans. Instrum. Meas., 2024

Resilient and Secure Programmable System-on-Chip Accelerator Offload.
CoRR, 2024

SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning.
Proceedings of the 2024 SIGCOMM Workshop on Networks for AI Computing, 2024

Low-Cost SCADA/HMI with Tiny Machine Learning for Monitoring Indoor CO2 Concentration.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2024

2023
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge.
ACM Trans. Reconfigurable Technol. Syst., September, 2023

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

Signal Detection for Large MIMO Systems Using Sphere Decoding on FPGAs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload.
Proceedings of the International Conference on Field Programmable Technology, 2023

Exploring FPGA Acceleration for Distributed Serverless Computing.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

REFL: Resource-Efficient Federated Learning.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023

2022
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation.
IEEE Trans. Parallel Distributed Syst., 2022

Correction to: Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder.
Neural Comput. Appl., 2022

Estimation of missing air pollutant data using a spatiotemporal convolutional autoencoder.
Neural Comput. Appl., 2022

High Throughput Multidimensional Tridiagonal Systems Solvers on FPGAs.
CoRR, 2022

FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL.
Proceedings of the IWOCL'22: International Workshop on OpenCL, Bristol, United Kingdom, May 10, 2022

High throughput multidimensional tridiagonal system solvers on FPGAs.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2021
Optimum Battery Weight for Maximizing Available Energy in UAV-Enabled Wireless Communications.
IEEE Wirel. Commun. Lett., 2021

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction.
Sensors, 2021

Resource-Efficient Federated Learning.
CoRR, 2021

High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

StressBench: A Configurable Full System Network and I/O Benchmark Framework.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Heterogeneous Communication Virtualization for Distributed Embedded Applications.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Toward Secure VMs Allocation: Analysis of VMs Allocation Behaviours in the Cloud Computing Environments.
Proceedings of the Cloud Computing and Services Science - 11th International Conference, 2021

Sit Here: Placing Virtual Machines Securely in Cloud Environments.
Proceedings of the 11th International Conference on Cloud Computing and Services Science, 2021

2020
High Throughput Spatial Convolution Filters on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Exploring hardware accelerator offload for the Internet of Things.
it Inf. Technol., 2020

A model for distributed in-network and near-edge computing with heterogeneous hardware.
Future Gener. Comput. Syst., 2020

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Characterizing Latency Overheads in the Deployment of FPGA Accelerators.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Quantifying the latency benefits of near-edge and in-network FPGA acceleration.
Proceedings of the 3rd International Workshop on Edge Systems, Analytics and Networking, 2020

2019
The Power-optimised Software Envelope.
ACM Trans. Archit. Code Optim., 2019

Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Neural Network Overlay Using FPGA DSP Blocks.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Network Intrusion Detection Using Neural Networks on FPGA SoCs.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Smart Network Interfaces for Advanced Automotive Applications.
IEEE Micro, 2018

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications.
ACM Comput. Surv., 2018

A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A time-multiplexed FPGA overlay with linear interconnect.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
Security in Automotive Networks: Lightweight Authentication and Authorization.
ACM Trans. Design Autom. Electr. Syst., 2017

Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA.
IEEE Trans. Computers, 2017

Fracturable DSP Block for Multi-context Reconfigurable Architectures.
Circuits Syst. Signal Process., 2017

High Throughput 2D Spatial Image Filters on FPGAs.
CoRR, 2017

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.
CoRR, 2017

An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration.
IEEE Access, 2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud.
IEEE Access, 2017

Metrics for Energy-Aware Software Optimisation.
Proceedings of the High Performance Computing - 32nd International Conference, 2017

In-network online data analytics with FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Design and Realization of Variable Digital Filters for Software-Defined Radio Channelizers Using an Improved Coefficient Decimation Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Mapping for Maximum Performance on FPGA DSP Blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Open source model and simulator for real-time performance analysis of automotive network security.
SIGBED Rev., 2016

Spectrally efficient emission mask shaping for OFDM cognitive radios.
Digit. Signal Process., 2016

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.
CoRR, 2016

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Improved resource sharing for FPGA DSP blocks.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Designing a virtual runtime for FPGA accelerators in the cloud.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Initiation Interval Aware Resource Sharing for FPGA DSP Blocks.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Throughput oriented FPGA overlays using DSP blocks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

Message from the ASAP 2016 chairs.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems.
IEEE Trans. Veh. Technol., 2015

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.
SIGARCH Comput. Archit. News, 2015

JIT trace-based verification for high-level synthesis.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Minimizing DSP block usage through multi-pumping.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

On Data Forwarding in Deeply Pipelined Soft Processors.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Efficient Overlay Architecture Based on DSP Blocks.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Lightweight authentication for secure automotive networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Security aware network controllers for next generation automotive embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Security analysis of automotive architectures using probabilistic model checking.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA.
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2015

Virtualized FPGA Accelerators for Efficient Cloud Computing.
Proceedings of the 7th IEEE International Conference on Cloud Computing Technology and Science, 2015

Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.
J. Signal Process. Syst., 2014

The iDEA DSP Block-Based Soft Processor for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2014

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq.
IEEE Embed. Syst. Lett., 2014

Robust and Efficient OFDM Synchronization for FPGA-Based Radios.
Circuits Syst. Signal Process., 2014

Shaping Spectral Leakage for IEEE 802.11p Vehicular Communications.
Proceedings of the IEEE 79th Vehicular Technology Conference, 2014

A case for leveraging 802.11p for direct phone-to-phone communications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

System simulation and optimization using reconfigurable hardware.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Zero latency encryption with FPGAs for secure time-triggered automotive networks.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Analysis and optimization of a deeply pipelined FPGA soft processor.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

DyRACT: A partial reconfiguration enabled accelerator and test platform.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient mapping of mathematical expressions into DSP blocks.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient multi-standard cognitive radios on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Square-rich fixed point polynomial evaluation on FPGAs.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Experiments in Mapping Expressions to DSP Blocks.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs.
Proceedings of the 2014 IEEE International Conference on Cyber-Physical Systems, 2014

A scalable and compact systolic architecture for linear solvers.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Architecture for Real-Time Nonparametric Probability Density Function Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Reconfigurable Computing in Next-Generation Automotive Networks.
IEEE Embed. Syst. Lett., 2013

Optimization of the HEFT Algorithm for a CPU-GPU Environment.
Proceedings of the International Conference on Parallel and Distributed Computing, 2013

Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

System-level FPGA device driver with high-level synthesis support.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Accelerating validation of time-triggered automotive systems on FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Enhancing communication on automotive networks using data layer extensions.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Iterative floating point computation using FPGA DSP blocks.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Efficient Large Integer Squarers on FPGA.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

An Approach to a Fully Automated Partial Reconfiguration Design Flow.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

An approach for redundancy in FlexRay networks using FPGA partial reconfiguration.
Proceedings of the Design, Automation and Test in Europe, 2013

System architecture and software design for electric vehicles.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Microkernel hypervisor for a hybrid ARM-FPGA platform.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
A high speed open source controller for FPGA Partial Reconfiguration.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

iDEA: A DSP block based FPGA soft processor.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Evaluating the efficiency of DSP Block synthesis inference from flow graphs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A lean FPGA soft processor built using a DSP block.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Embedded systems and software challenges in electric vehicles.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
A Model-Based Approach to Cognitive Radio Design.
IEEE J. Sel. Areas Commun., 2011

Efficient region allocation for adaptive partial reconfiguration.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A threat-based Connect6 implementation on FPGA.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Enabling high level design of adaptive systems with partial reconfiguration.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
Iris: an architecture for cognitive radio networking testbeds.
IEEE Commun. Mag., 2010

Histogram-based probability density function estimation on FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds.
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
High-throughput one-dimensional median and weighted median filters on FPGA.
IET Comput. Digit. Tech., 2009

Development Framework for Implementing FPGA-Based Cognitive Network Nodes.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Generic Software Framework for Adaptive Applications on FPGAs.
Proceedings of the FCCM 2009, 2009

2008
Hardware acceleration of the trace transform for vision applications.
PhD thesis, 2008

Generalised Parallel Bilinear Interpolation Architecture for Vision Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Real-time hardware acceleration of the trace transform.
J. Real Time Image Process., 2007

2006
Efficient Realtime FPGA Implementation of the Trace Transform.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Investigating Trace Transform Architectures for Face Authentication.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.
Proceedings of the 2005 Design, 2005


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