Rama Sangireddy

According to our database, Rama Sangireddy authored at least 25 papers between 2001 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2010

Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding.

Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy

Proceedings of the 39th International Conference on Parallel Processing, 2010

2009

Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors.

Hui Wang, Rama Sangireddy, Sandeep Baldawa

IEEE Trans. Parallel Distributed Syst., 2009

2008

Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC.

Rama Sangireddy, Jatan P. Shah

IEEE Trans. Parallel Distributed Syst., 2008

Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution.

Hui Wang, Rama Sangireddy

Microprocess. Microsystems, 2008

Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.

Hui Wang, Sandeep Baldawa, Rama Sangireddy

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies.

Terrell R. Bennett, Rama Sangireddy

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Register port complexity reduction in wide-issue processors with selective instruction execution.

Rama Sangireddy

Microprocess. Microsystems, 2007

Scalable Reconfigurable Architectures for High-Performance Energy-Efficient Multimedia Processing.

Rama Sangireddy, Prabhu Rajamani

Int. J. Comput. Their Appl., 2007

Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering.

Jatan P. Shah, Rama Sangireddy

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

On-Chip Adaptive Circuits for Fast Media Processing.

Rama Sangireddy, Arun K. Somani

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.

Rama Sangireddy

IEEE Trans. Computers, 2006

Performance Optimization with Scalable Reconfigurable Computing Systems.

Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors.

Rama Sangireddy

Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Fast and low-power processor front-end with reduced rename logic circuit complexity.

Rama Sangireddy

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization.

Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy

Proceedings of the 25th IEEE International Performance Computing and Communications Conference, 2006

2005

Scalable, memory efficient, high-speed IP lookup algorithms.

Rama Sangireddy, Natsuhiko Futamura, Srinivas Aluru, Arun K. Somani

IEEE/ACM Trans. Netw., 2005

2004

Low-Power High-Performance Reconfigurable Computing Cache Architectures.

Rama Sangireddy, Huesung Kim, Arun K. Somani

IEEE Trans. Computers, 2004

Exploiting Quiescent States in Register Lifetime.

Rama Sangireddy, Arun K. Somani

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Register Organization for Enhanced On-Chip Parallelism.

Rama Sangireddy

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003

High-speed IP routing with binary decision diagrams based hardware address lookup engine.

Rama Sangireddy, Arun K. Somani

IEEE J. Sel. Areas Commun., 2003

Scalable, memory efficient, high-speed lookup and update algorithms for IP routing.

Natsuhiko Futamura, Rama Sangireddy, Srinivas Aluru, Arun K. Somani

Proceedings of the 12th International Conference on Computer Communications and Networks, 2003

Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures.

Rama Sangireddy, Huesung Kim, Arun K. Somani

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

Application-Specific Computing with Adaptive Register File Architectures.

Rama Sangireddy, Arun K. Somani

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing.

Rama Sangireddy, Huesung Kim, Arun K. Somani

Proceedings of the High Performance Computing, 2002

2001

Binary decision diagrams for efficient hardware implementation of fast IP routing lookups.

Rama Sangireddy, Arun K. Somani

Proceedings of the 10th International Conference on Computer Communications and Networks, 2001