Ranganathan Sankaralingam

According to our database, Ranganathan Sankaralingam authored at least 6 papers between 2000 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2010

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation.

Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam

Proceedings of the 2011 IEEE International Test Conference, 2010

2002

Controlling Peak Power During Scan Testing.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Inserting Test Points to Control Peak Power During Scan Testing.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Reducing Test Power During Test Using Programmable Scan Chain Disable.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Reducing Power Dissipation during Test Using Scan Chain Disable.

Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Static Compaction Techniques to Control Scan Vector Power Dissipation.

Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000