Shuou Nomura

According to our database, Shuou Nomura authored at least 9 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency.

Takumi Fujimori, Shuou Nomura

Proceedings of the 16th ACM International Conference on Systems and Storage, 2023

2021

Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications.

Tomoya Suzuki, Kazuhiro Hiwada, Hirotsugu Kajihara, Shintaro Sano, Shuou Nomura, Tatsuo Shiozawa

Proc. VLDB Endow., 2021

2011

Sampling + DMR: practical and low-overhead permanent fault detection.

Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, Karthikeyan Sankaralingam

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation.

Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam

Proceedings of the 2011 IEEE International Test Conference, 2010

Relax: an architectural framework for software recovery of hardware faults.

Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism.

Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam

Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

2008

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design.

Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.

Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama

IEEE J. Solid State Circuits, 2006