Rani S. Ghaida

According to our database1, Rani S. Ghaida authored at least 12 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
Pattern-restricted design at 10nm and beyond.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Comprehensive die-level assessment of design rules and layouts.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Layout Decomposition and Legalization for Double-Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Role of design in multiple patterning: technology development, design enablement and process control.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A methodology for the early exploration of design rules for multiple-patterning technologies.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
A framework for double patterning-enabled design.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Electrical Modeling of Lithographic Imperfections.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects.
J. Electron. Test., 2009

A framework for early and systematic evaluation of design rules.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2007
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007


  Loading...