Payman Zarkesh-Ha

According to our database1, Payman Zarkesh-Ha authored at least 45 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Face Recognition on a Smart Image Sensor Using Local Gradients.
Sensors, 2021

2020
5.2dB Sensitivity Enhancement in 25Gbps APD-Based Optical Receiver using Dynamic Biasing.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

Impact of Memristor Defects in a Neuromorphic Radionuclide Identification System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Wavelet-based convolutional neural networks for gender classification.
J. Electronic Imaging, 2019

SRAM Physically Unclonable Functions Implemented on Silicon Germanium.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017
A meter-scale 600-Mb/s 2×2 imaging MIMO OOK VLC link using commercial LEDs and Si p-n photodiode array.
Proceedings of the 26th Wireless and Optical Communication Conference, 2017

A robust 2×2 CMOS receiver array for meter-scale point-to-point OOK VLC links.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

The effect of power supply ramp time on SRAM PUFs.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Analytical noise model for avalanche ISFET sensor suitable for Next Generation Sequencing.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Behavioral modeling of drain current of an avalanche ISFET near breakdown.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
Avalanche ISFET: A highly sensitive pH sensor for genome sequencing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Evaluating mobile SOCs as an energy efficient DSP platform.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

An intelligent readout circuit for infrared multispectral remote sensing.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A novel readout circuit for on-sensor multispectral classification.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Multi-wavelength visible light communication system design.
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 8-12, 2014, 2014

2013
Spatio-temporal tunable pixels for multi-spectral infrared imagers.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
Comparison of variations in MOSFET versus CNFET in gigascale integrated systems.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Prediction of gate delay variation for CNFET under CNT density variation.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Reducing energy and increasing performance with traffic optimization in many-core systems.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010
Hybrid network on chip (HNoC): local buses with a global mesh architecture.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Modeling NoC traffic locality and energy consumption with rent's communication probability distribution.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

A robust and low power dual data rate (DDR) flip-flop using c-elements.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A linear digital VCO for Clock Data Recovery (CDR) applications.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Logic Gate Failure Characterization for Nanoelectronic EDA Tools.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects.
J. Electron. Test., 2009

2008
Analytical Noise-Rejection Model Based on Short Channel MOSFET.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Stochastic interconnect layout sensitivity model.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2004
Global interconnect design in a three-dimensional system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Prediction of interconnect adjacency distribution: derivation, validation, and applications.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003
Prediction of interconnect pattern density distribution: derivation, validation, and applications.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Interconnect opportunities for gigascale integration.
IBM J. Res. Dev., 2002

2001
Impact of three-dimensional architectures on interconnects in gigascale integration.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2000

A compact physical via blockage model.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Prediction of interconnect fan-out distribution using Rent's rule.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000


  Loading...