Sani R. Nassif

According to our database1, Sani R. Nassif authored at least 146 papers between 1984 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2008, "For contributions to semiconductor manufacturing processes".

Timeline

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Bibliography

2019
SRAM Design Exploration with Integrated Application-Aware Aging Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2015
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Editorial.
IET Comput. Digit. Tech., 2015

Analysis and optimization of flip-flops under process and runtime variations.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014

Statistical analysis of process variation induced SRAM electromigration degradation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Opportunities in power distribution network system optimization: from EDA perspective.
Proceedings of the International Symposium on Physical Design, 2014

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Applying VLSI EDA to energy distribution system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Layout Decomposition and Legalization for Double-Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro, 2013

Keynote 1 - VLSI 2.0: R&D Post Moore.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Wire delay variability in nanoscale technology and its impact on physical design.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM bit-line electromigration mechanism and its prevention scheme.
Proceedings of the International Symposium on Quality Electronic Design, 2013

SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

ICCAD-2013 CAD contest in mask optimization and benchmark suite.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo.
Proceedings of the International Conference on Computational Science, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.
Proceedings of the 18th IEEE European Test Symposium, 2013

Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.
Proceedings of the European Solid-State Device Research Conference, 2013

Incorporating the impacts of workload-dependent runtime variations into timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
An accurate sparse-matrix based framework for statistical static timing analysis.
Integr., 2012

An oscillation-based test structure for timing information extraction.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Design-aware lithography.
Proceedings of the International Symposium on Physical Design, 2012

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2012 TAU power grid simulation contest: Benchmark suite and results.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Yield estimation via multi-cones.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
The Impact of Statistical Leakage Models on Design Yield Estimation.
VLSI Design, 2011

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness.
IEEE Trans. Very Large Scale Integr. Syst., 2011

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Hierarchical Multialgorithm Parallel Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Simultaneous Layout Migration and Decomposition for Double Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Efficient and product-representative timing model validation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Coupling timing objectives with optical proximity correction for improved timing yield.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Ultra-low power current-based PUF.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2011 TAU power grid simulation contest: Benchmark suite and results.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Accelerated statistical simulation via on-demand Hermite spline interpolations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A framework for double patterning-enabled design.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Electrically-driven retargeting for nanoscale layouts.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Post-Silicon Timing Validation Method Using Path Delay Measurements.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

'Tis the gift to be simple.
IEEE Des. Test Comput., 2010

Physical design challenges beyond the 22nm node.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Template-mask design methodology for double patterning technology.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A resilience roadmap.
Proceedings of the Design, Automation and Test in Europe, 2010

A methodology for propagating design tolerances to shape tolerances for use in manufacturing.
Proceedings of the Design, Automation and Test in Europe, 2010


The light at the end of the CMOS tunnel.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
The impact of BEOL lithography effects on the SRAM cell performance and yield.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Yield estimation of SRAM circuits using "Virtual SRAM Fab".
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Analyzing the impact of process variations on parametric measurements: Novel models and applications.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Power Grid Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Model to Hardware Matching for nm Scale Technologies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A Design Model for Random Process Variability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Root-Finding Method for Assessing SRAM Stability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

MAPS: multi-algorithm parallel circuit simulation.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.
Proceedings of the Design, Automation and Test in Europe, 2008

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.
Proceedings of the 45th Design Automation Conference, 2008

Characterization and design for variability and reliability.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Process variability at the 65nm node and beyond.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Analytical model for the impact of multiple input switching noise on timing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Power grid analysis benchmarks.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Technology modeling and characterization beyond the 45nm node.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Design for Manufacturability and Statistical Design - A Constructive Approach.
Series on integrated circuits and systems, Springer, ISBN: 978-0-387-30928-6, 2008

2007
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Estimating path delay distribution considering coupling noise.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
Proceedings of the 44th Design Automation Conference, 2007

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
Proceedings of the 44th Design Automation Conference, 2007

Characterizing Process Variation in Nanometer CMOS.
Proceedings of the 44th Design Automation Conference, 2007

2006
High-performance CMOS variability in the 65-nm regime and beyond.
IBM J. Res. Dev., 2006

Guest Editors' Introduction: Process Variation and Stochastic Design and Test.
IEEE Des. Test Comput., 2006

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

System-Level SRAM Yield Enhancement.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SRAM Local Bit Line Access Failure Analyses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Model to hardware matching: for nano-meter scale technologies.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Methods for estimating decoupling capacitance of nonswitching circuit blocks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Characterization of total chip leakage using inverse (reciprocal) gamma distribution.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Analytical modeling of SRAM dynamic stability.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Variation-aware analysis: savior of the nanometer era?
Proceedings of the 43rd Design Automation Conference, 2006

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
Proceedings of the 43rd Design Automation Conference, 2006

Statistical analysis of SRAM cell stability.
Proceedings of the 43rd Design Automation Conference, 2006

Circuit Optimization Using Scale Based Sensitivities.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Power grid analysis using random walks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Early-stage power grid analysis for uncertain working modes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Leakage and Leakage Sensitivity Computation for Combinational Circuits.
J. Low Power Electron., 2005

Power Variability and Its Impact on Design.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Testing and debugging delay faults in dynamic circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A More Effective C<sub>EFF</sub>.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An efficient surface-based low-power buffer insertion algorithm.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Power-aware global signaling strategies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Benefits and Costs of Power-Gating Technique.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.
Proceedings of the 2005 Design, 2005

The Titanic: what went wrong!
Proceedings of the 42nd Design Automation Conference, 2005

2004
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Impact of Design-Manufacturing Interface on SoC Design Methodologies.
IEEE Des. Test Comput., 2004

Approaches to run-time and standby mode leakage reduction in global buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

The impact of variability on power.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A chip-level electrostatic discharge simulation strategy.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

The care and feeding of your statistical static timer.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Variational delay metrics for interconnect timing analysis.
Proceedings of the 41th Design Automation Conference, 2004

2003
Optimal decoupling capacitor sizing and placement for standard-cell layout designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Guest Editors' Introduction: On-Chip Power Distribution Networks.
IEEE Des. Test Comput., 2003

Optimal shielding/spacing metrics for low power design.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Full chip leakage estimation considering power supply and temperature variations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Leakage and leakage sensitivity computation for combinational circuits.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Power grid reduction based on algebraic multigrid principles.
Proceedings of the 40th Design Automation Conference, 2003

Random walks in a supply network.
Proceedings of the 40th Design Automation Conference, 2003

Predicting short circuit power from timing models.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A multigrid-like technique for power grid analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test structures for delay variability.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Technology trends in power-grid-induced noise.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Impact of Technology in Power-Grid-Induced Noise.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Time-Domain Simulation of Variational Interconnect Models.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
Proceedings of 2002 International Symposium on Physical Design, 2002

Static timing analysis based circuit-limited-yield estimation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Linear-Centric Simulation Framework for Parametric Fluctuations.
Proceedings of the 2002 Design, 2002

Congestion-driven codesign of power and signal networks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Timing Yield Estimation from Static Timing Analysis.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

I/O buffer placement methodology for ASICs.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
Proceedings of ASP-DAC 2001, 2001

Modeling and forecasting of manufacturing variations (embedded tutorial).
Proceedings of ASP-DAC 2001, 2001

2000
Design for Variability in DSM Technologies.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Multi-grid methods for power grid simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Designing Closer to the Edge.
Proceedings of the 2000 Design, 2000

Fast power grid simulation.
Proceedings of the 37th Conference on Design Automation, 2000

When bad things happen to good chips (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.
Proceedings of the 37th Conference on Design Automation, 2000

Impact of interconnect variations on the clock skew of a gigahertz microprocessor.
Proceedings of the 37th Conference on Design Automation, 2000

1999
SOI technology and tools (abstract).
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1997
Physical design challenges for performance.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1986
A Methodology for Worst-Case Analysis of Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

CINNAMON: coupled integration and nodal analysis of MOS networks.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984
FABRICS II: A Statistically Based IC Fabrication Process Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

DIF: A framework for VLSI multi-level representation.
Integr., 1984


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