Ratan Nalumasu

According to our database1, Ratan Nalumasu authored at least 6 papers between 1997 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2002
An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation.
Formal Methods Syst. Des., 2002

Deriving Efficient Cache Coherence Protocols Through Refinement.
Formal Methods Syst. Des., 2002

1998
Using "Test Model-Checking" to Verify the Runway-PA8000 Memory Model.
Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, 1998

PV: An Explicit Enumeration Model-Checker.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
Formal modeling and validation applied to a commercial coherent bus: a case study.
Proceedings of the Advances in Hardware Design and Verification, 1997


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