Ravi Hosabettu

According to our database1, Ravi Hosabettu authored at least 8 papers between 1997 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2003
Formal Verification of a Complex Pipelined Processor.
Formal Methods Syst. Des., 2003

A Practical Methodology for Verifying Pipelined Microarchitectures.
IEEE Des. Test Comput., 2003

2000
Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem.
Formal Methods Syst. Des., 2000

Verifying Advanced Microarchitectures that Support Speculation and Exceptions.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

Decomposing the Proof of Correctness of pipelined Microprocessors.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
Formal modeling and validation applied to a commercial coherent bus: a case study.
Proceedings of the Advances in Hardware Design and Verification, 1997


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