Ravi S. Siddanath

According to our database¹, Ravi S. Siddanath authored at least 2 papers between 2024 and 2025.

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2025

High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset.

[BibT_eX]

[DOI]

Integr., 2024