Ravi S. Siddanath

According to our database, Ravi S. Siddanath authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Design of Hybrid, High-Speed, Nonvolatile Ternary Content Addressable Memory Using CMOS and RRAM.

Mohit Gupta, Ravi S. Siddanath, Layak Singh Yadav, Mudit Gupta, Manish Goswami, Kavindra Kandpal

J. Circuits Syst. Comput., 2026

A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes.

Ravi S. Siddanath, Sukhen Mondal, Manish Goswami, Kavindra Kandpal

IEEE Access, 2026

2025

High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology.

Ravi S. Siddanath, Mohit Gupta, R. Dhirendra Rao, Souvik Kumar Das, Raghavendra Manjunath Hegde, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Energy-Efficient, Nonvolatile 8T-2MTJ Ternary CAM Cell for Low Search Delay.

Mohit Gupta, Ravi S. Siddanath, Mudit Gupta, Surya Prakash, Manish Goswami, Kavindra Kandpal

Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset.

Ravi S. Siddanath, Mohit Gupta, Chaitanya Joshi, Manish Goswami, Kavindra Kandpal

Integr., 2024