Raymond Mabilangan

According to our database, Raymond Mabilangan authored at least 5 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS.

Bo Gao, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

A SAR-Assisted Continuous-Time M-0 MASH Delta-Sigma Modulator With Digital-Domain Noise Leakage Shaping.

Kent Edrian Lozada, Bo Gao, Raymond Mabilangan, Charlie Tahar, Kun-Woo Park, Young-Hun Moon, Kwan-Hoon Song, Seung-Tak Ryu

IEEE Open J. Circuits Syst., 2026

2024

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation.

Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, Seung-Tak Ryu

IEEE Open J. Circuits Syst., 2024

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA.

Bo Gao, Lizhen Zhang, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2021

An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation.

Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021