Youngjae Cho

Orcid: 0009-0000-6021-6813

Affiliations:
  • Samsung Electronics, Seoul, Korea
  • Sogang University, Department of Electronic Engineering, Seoul, Korea (PhD 2007)


According to our database1, Youngjae Cho authored at least 26 papers between 2004 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

2025
A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS.
IEEE J. Solid State Circuits, April, 2025

2024
High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling.
IEEE J. Solid State Circuits, October, 2024

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3<sup>rd</sup>-Order Noise Coupling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3<sup>rd</sup>-Order SAR-Assisted CT DSM with 1-0 MASH and DNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2007
A 10 b 200 MS/s 1.8 mm<sup>2</sup> 83 mW 0.13µm CMOS ADC Based on Highly Linear Integrated Capacitors.
IEICE Trans. Electron., 2007

2006
A 10b 100 MS/s 1.4 mm<sup>2</sup>56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors.
IEICE Trans. Electron., 2006

An Embedded 8b 240 MS/s 1.36 mm<sup>2</sup> 104 mW 0.18 µCMOS ADC for DVDs with Dual-Mode Inputs.
IEICE Trans. Electron., 2006

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
An 11b 70-MHz 1.2-mm<sup>2</sup> 49-mW 0.18-μm CMOS ADC with on-chip current/voltage references.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References.
IEICE Trans. Electron., 2005

An 8b 240 MS/s 1.36 mm<sup>2</sup> 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth.
IEEE J. Solid State Circuits, 2004


  Loading...